先端半導体パッケージング・実装技術の研究開発動向

昨今、特に話題を集める半導体パッケージングですが、これに関連した数ある国際会議の中でも最も大きく最新の技術が発表されるのがECTC (Electronic Components and Technology Conference) です。 　今回のセミナーでは、半導体パッケージングの最新動向を紹介し、2024年5月に終えたECTC2024の中からチップレット/インターポーザやラージパネル、ハイブリッド接合および光電融合などを中心にハイライトを行います。ECTC2024の総発表件数389件 (ポスター137件含む) から83件の注目発表をピックアップして解説する予定です。

1. ECTCの紹介と最近の研究動向、および用語の説明
   1. ECTCの発表件数の推移や国別/研究機関別投稿状況
   2. 先端半導体パッケージングの分類や動向
   3. ハイブリッド接合の概要
2. チップレット/インターポーザ/ラージパネル 7件
   • Session 1: Advances in Fan-Out, Wafer-Level, and Panel-Level Packaging Technologies Enabling New Applications
     • Paper 1. How to Manipulate Warpage in Fan-Out Wafer and Panel Level Packaging
       (Fraunhofer IZM/TU Berlin)
     • Paper 4. 600 mm x 600 mm Fan-Out Panel Level Package (FOPLP) as an Alternative to Lead-Frame-Free Quad Flat No Lead (QFN) Package (NEPES/Deca)
     • Paper 5. Challenges and Analysis for Pitch 25 μm-100 μm Mixed Micro Bumps and Interconnection in Fan-Out Embedded and Interconnection in Fan-Out Embedded Bridge Die With TSV Package (FO-EB-TSV) (SPIL)
   • Session 7: Heterogeneous Integration: Systems Design, Signal & Power Delivery, and Process Optimization
     • Paper 1. Next Generation Large Size High Interconnect Density CoWoS-R Package (TSMC)
   • Session 16: Reliability of High-Density and High-Power Packages
     • Paper 2. Reliability Investigations of Advanced Photosensitive Polymer Based RDL Processes Protected by Inorganic Capping Layers (imec/Veeco)
   • Session 19: 3D Integration Copper-Copper Hybrid Bonding
     • Paper 6. 3.5D Advanced Packaging Enabling Heterogenous Integration of HPC and AI Accelerators
       (AMD)
   • Session 26: Chiplet Interconnect Design and Validation
     • Paper 7. Signal Integrity Designs at Organic Interposer CoWoS-R for HBM3-9.2Gbps High Speed Interconnection of 2.5D-IC Chiplets Integration (Global Unichip Corporation)
3. ハイブリッド接合 70件
   • Session 2: Advanced Die-to-Wafer Hybrid Bonding for Heterogeneous Integration
     • Paper 1. Direct Die-to-Wafer Hybrid Bonding Using Plasma Diced Dies and Bond Pad Pitch Scaling Down to 2 μm (imec)
     • Paper 2. Multi-Functional Self-Assembled Monolayer (SAM) for Chip-to-Chip and Chip-to-Wafer Hybrid Bonding Yield Enhancement (Tohoku University/T-Micro/JX Metals)
     • Paper 3. 3D Heterogeneous IntegrationWith Sub-3 μm Bond Pitch Chip-to-Wafer Hybrid Bonding
       (Intel)
     • Paper 4. Novel Three-Layer Stacking Process With Face-To-Back CoW 6 μm-Pitch Hybrid Bonding
       (Sony)
     • Paper 5. Dielectric Stack Optimization for Die-Level Warpage Reduction for Chip-to-Wafer Hybrid Bonding (IME A*STAR)
     • Paper 6. Low Temperature Wafer Level Hybrid Bonding Enabled by Advanced SiCN and Surface Activation (Yokohama National University/TEL/SK Hynix)
     • Paper 7. A Study on D2W Hybrid Cu Bonding Technology for HBM Multi-Die Stacking (Samsung)
   • Session 8: Sub-Micron Scaling in Wafer-to-Wafer Hybrid Bonding
     • Paper 1. Study of Ultra Fine 0.4 μm Pitch Wafer-to-Wafer Hybrid Bonding and Impact of Bonding Misalignment (Sony)
     • Paper 2. 3-Layer Fine Pitch Cu-Cu Hybrid Bonding Demonstrator With High Density TSV for Advanced CMOS Image Sensor Applications (Grenoble Alps University/CEA-LETI)
     • Paper 3. Scaling Cu/SiCN Wafer-to-Wafer Hybrid Bonding Down to 400 nm Interconnect Pitch
       (imec)
     • Paper 4. Fine Pitch and Low Temperature Nanocrystalline-Nanotwinned Cu and SiCN-to-SiO2 Wafer-to-Wafer Hybrid Bonding (ITRI / Nanya Technology)
     • Paper 5. Single-Grain Cu μ-Joint Formation Directed by Selective Under-Seed-Metallurgy (USM) for Hybrid Bonding (Tohoku Univ./T-Micro/JCU)
     • Paper 6. 0.5 μm Pitch Wafer-to-Wafer Hybrid Bonding at Low Temperatures With SiCN Bond Layer
       (AMAT/EVG)
     • Paper 7. Development of Double Cantilever Beam Technique for Wafer-to-Wafer Bond Energy Measurement (Micron Technology)
   • Session 10: Novel 3D Integration and Hybrid Bonding Solutions
     • Paper 1. Investigation of Distortion in Wafer-to-Wafer Bonding with Highly Bowed Wafers
       (imec/EVG)
     • Paper 2. Development of 0.5 μm Pixel 3-Wafers Stacked CMOS Image Sensor With Through Silicon Deep Contact and In-Pixel Cu-to-Cu Bonding Process (Samsung)
     • Paper 3. Non-TCB Process Cu/SiO2 Hybrid Bonding Using Plasma-Free Hydrophilicity Enhancement With NaOH for Chip-to-Wafer Bonding (National Yang Ming Chiao Tung University / ITRI)
     • Paper 4. Novel Low Thermal Budget Bonding Using Single Wafer Thermal Processing System, Resulting in Excellent Wafer-to-Wafer Hybrid Bonding at sub 0.5um Pitch (AMAT)
     • Paper 7. D2W Hybrid Bonding System Achieving Both High-Accuracy and High Throughput With Minimal Configuration (Toray Engineering/Tohoku University/YNU/University of Tsukuba)
   • Session 11: Next-Generation Artificial Intelligence, Quantum Computing, and Secure Packaging
     • Paper 3. Fine Pitch Nb-Nb Direct Bonding for Quantum Applications
       (Grenoble Alps University/CEA-LETI)
   • Session 12: Artificial Intelligence and Advanced Modeling Approaches
     • Paper 4. Deep Convolution Neural Networks for Automatic Detection of Defects Which Impact Hybrid Bonding Yield (Adeia)
   • Session 15: Novel Materials and Process for Hybrid Bonding
     • Paper 1. Towards Standardization of Hybrid Bonding Interface: In-Depth Study of Dielectrics on Direct Bonding (Intel /Arizona State University/Washington State University)
     • Paper 2. Demonstration of Low Temperature Cu-Cu Hybrid Bonding Using a Novel Thin Polymer
       (Mitsui Chemicals)
     • Paper 3. Process Challenges in Thin Wafers Fabrication With Double Side Hybrid Bond Pads for Chip Stacking (IME A*STAR)
     • Paper 4. Development of Low Temperature Processable Polyimides for Organic Hybrid Bonding Applications (Toray / Toray Singapore Research Center)
     • Paper 5. Effect of (111) Surface Ratio on the Bonding Quality of Cu-Cu Joints
       (National Yang Ming Chiao Tung University)
     • Paper 6. Copper Microstructure Optimization for Fine Pitch Low Temperature Cu/SiO2 Hybrid Bonding (Grenoble Alps University/CEA-LETI)
     • Paper 7. Multi-Tier Die Stacking Through Collective Die-to-Wafer Hybrid Bonding
       (imec/Brewer Science/SUSS MicroTec)
   • Session 18: Radio Frequency Antenna-in-Package and Component Design
     • Paper 6. RF Modelling and Characterization of TSV and Inductive Links of Hybrid Bonding (imec)
   • Session 19: 3D Integration Copper-Copper Hybrid Bonding
     • Paper 1. A Study of Low Temperature SoIC Targeting 200 nm Bond Pitch (TSMC)
     • Paper 2. Low Resistance and High Isolation HD TSV for 3-Layer CMOS Image Sensors
       (Grenoble Alps University/CEA-LETI)
     • Paper 3. Integrated Hybrid Bonding System for the Next Generation Advanced 3D Packaging
       (AMAT/Besi)
     • Paper 4. Process Development and Performance Benefits of 0.64 μm-0.36 μm Pitch Hybrid Bonding on Intel Process (Intel)
     • Paper 5. Methodologies for Characterization of W2W Bonding Strength (imec)
     • Paper 7. Facile Wafer-to-Wafer Hybrid Bonding Integration at Sub 0.5 μm Pitch (IME A*STAR)
   • Session 21: Innovations in Polymer Packaging Materials
     • Paper 4. Low-Temperature Polymer Hybrid Bonding With Nanopaticulated Cu and Photosensitive Acrylic Adhesive (Daicel /T-Micro/Tohoku University)
   • Session 23: Novel Bonding Technology for Advanced Assembly Substrates and Integration
     • Paper 7. High-Throughput Characterization of Nanoscale Topography for Hybrid Bonding by Optical Interferometry (Adeia)
   • Session 26: Chiplet Interconnect Design and Validation
     • Paper 1. Impact of Pitch Scaling on 3D Die-to-Die Interconnects (imec)
   • Session 30: Process and Hybrid Bonding Modeling and Characterization
     • Paper 1. Modeling of Copper Hybrid Bonding Anneal (TEL)
     • Paper 3. Elucidating the Mechanism of Four Corner Voids in Chip-on-Wafer Hybrid Bonding (Sony)
     • Paper 6. Finite Element Modeling for Wafer-to-Wafer Direct Bonding Behaviors and Alignment Prediction (Samsung)
   • Session 32: Advancement in Copper Hybrid Bonding Technologies Common to Multiple Applications
     • Paper 1. A Microstructural Investigation of Sub-1 μm Copper Bonding Contact Structures in Die-to-Wafer Hybrid Bonding (State Univ. of New York at Binghamton/IBM)
     • Paper 2. Low-Temperature Cu-Cu Bonding Using <111>-Oriented and Nanocrystalline Hybrid Surface Grains (National Yang Ming Chiao Tung University / ITRI)
     • Paper 4. Achieving Sub-nm Copper Recess Controllability for Advanced 3D Integration: An Experimental and Atomic-scale Simulation Study on Wet Atomic Layer Etching Process
       (Samsung)
     • Paper 5. Quantifying the Electrical Impact of Bonding Misalignment for 0.5 μm Pitch Hybrid Bonding Structures (TEL America)
     • Paper 6. Liquid Surface Tension-Driven Chip Self-Assembly Technology With Cu-Cu Hybrid Bonding for High-Precision and High-Throughput 3D Stacking of DRAM
       (Tohoku Univ./Yamaha Robotics Holdings)
     • Paper 7. Wafer-on-Wafer-on-Wafer (WoWoW) Integration Having Large-Scale High Reliability Fine 1 μm Pitch Face-to-Back (F2B) Cu-Cu Connections and Fine 6 μm Pitch TSVs (Sony)
   • Interactive Session (これ以降はポスター発表です)
   • Session 37: Thermo-mechanical Stress and Reliability Analysis for Materials in Future Packaging
     • Paper 6. Multiphysics Overlay Modeling of Monolithic 3D Fusion and Hybrid Bonding Processes
       (EVG)
     • Paper 17. Thermal Transport Properties of Hybrid Bonding With Passivation
       (Seoul National University/Seoul National University of Science and Technology)
     • Paper 20. Method to evaluate the adhesion distribution on wafers (Sony)
     • Paper 21. Experimental and Numerical Investigation of Cu-Cu Direct Bonding Quality for 3D Integration (Sungkyunkwan University/BASF)
     • Paper 22. Atomistic Simulation Investigation of Various Plasma Surface Activations in SiCN Dielectric Bonding (TEL)
   • Session 38: Photonics, mm-Wave Applications & Emerging Technologies
     • Paper 14. All-Cu 3D Interconnects as an Alternative to Hybrid Bonding (Meisei University)
   • Session 39: Bonding Process and Analysis in Next-generation Interconnects
     • Paper 2. Hybrid Bonding Technology Chemical Mechanical Planarization Process Optimization Using Comprehensive 3D Modeling (AMAT/Synopsys)
     • Paper 5. A Study on the Surface Activation of Plasma Treatment for Hybrid Bonding Joint Interface (ASE)
     • Paper 7. Inverse Hybrid Bonding With Aluminum Oxide as Infill Using Atomic Layer Deposition
       (Georgia Tech./UCSD)
     • Paper 12. Low Temperature Nanocrystalline Cu/Polymer Hybrid Bonding With Tailored CMP Process (ITRI/Brewer Science)
     • Paper 15. Low Thermal Budget Fine-Pitch Cu/Dielectric Hybrid Bonding With Cu Microstructure Modifications (IME A*STAR)
     • Paper 21. Low Temperature Cu/SiO2 Hybrid Bonding With Protruding Copper Pads
       (Tsinghua University/SMIB: Semiconductor Technology Innovation Center (Beijing) Corporation)
     • Paper 22. Analysis of vacancies in Wafer-Bonding Interface Via Positron Annihilation Lifetime Spectroscopy (Sony)
     • Paper 23. Annealing Effects in Sub-8 μm Pitch Die-to-Wafer Hybrid Bonding
       (TEL America/Fraunhofer IZM/SkyWater Technology/BRIDG)
     • Paper 27. Aluminum-to-Aluminum and Aluminum-to-Copper Thermal Compression Bonding for Heterogeneous Integration of Legacy Dielets (UCLA)
     • Paper 29. Exploring Bonding Mechanisms of SiCN for Hybrid Bonding
       (Yokohama National University/imec/University of Tsukuba)
   • Session 40: Materials, Manufacturing and Assembly Techniques in Advanced Packaging Solutions
     • Paper 8. Comparison of Organic and Inorganic Dielectric Hybrid Bonding With Highly
       h4. 第111部.-Oriented Nanotwinned Cu (National Yang Ming Chiao Tung University)
     • Paper 13. Multi Chip Stacked Memory Module Development Using Chip to Wafer (C2W) Hybrid Bonding for Heterogeneous Integration Applications (IME A*STAR)
     • Paper 15. Fluidic Self Alignment for Hybrid Bonding Using Intel Process (Intel)
     • Paper 16. An Advanced Remote-Plasma Assisted Ozone-Ethylene-Radical (OER) Process for Cu-SiO2 Hybrid Bonding Yield Enhancement
       (Meiden Nanoprocess Innovations / Tohoku Univ.)
     • Paper 19. A CMP Process for Hybrid Bonding Application With Conventional / nt-Cu and SixNy / SixOy Dielectrics (Intel / AMAT)
     • Paper 26. Room-Temperature Hybrid Bonding of Via-Middle TSV Wafer Fabricated by Direct Si/Cu Grinding and Residual Metal Removal (AIST/Okamoto Machine Tool Works)
   • Session 41: Student Posters
     • Paper 1. Low Temperature Cu/SiO2 Hybrid Bonding Using Area-Selective Metal Passivation
       (Interface Metal) Technology for 3D IC and Advanced Packaging
       (National Yang Ming Chiao Tung University/ITRI)
4. 光電融合 (Co-PKG) 6件
   • Session 3: Co-Packaged Optics
     • Paper 1. High Density Integration of Silicon Photonic Chiplets for 51.2T Co-packaged Optics
       (Broadcom/SPIL)
     • Paper 3. A surface-mount photonic package with a photonic-wire-bonded glass interposer as a hybrid integration platform for co-packaged optics
       (Sumitomo Electric/FICT/Tokyo Institute of Technology)
     • Paper 4. Development of all-photonics-function embedded package substrate using 2.3D RDL interposer for co-packaged optics (AIST/Kyocera)
     • Paper 5. Advanced 3D Packaging of 3.2Tbs Optical Engine for Co-packaged Optics (CPO) in Hyperscale Data Center Networks (Cisco Systems)
   • Session 22: Signal & Power Integrity for Advanced Packages and Systems
     • Paper 1. High Bandwidth and Energy Efficient Electrical-Optical System Integration Using COUPE Technology (TSMC)
   • Session 34: Photonics Integration, Materials, and Processes
     • Paper 3. A Compact Wafer-Level Heterogeneously Integrated Scalable Optical Transceiver for Data Centers (IME A*STAR/Marvell)
• 質疑応答