先端半導体パッケージの開発動向と材料・プロセス技術

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オンライン 開催

本セミナーでは、2021年7月に終えた国際会議 ECTC 2021の中からチップレット、3D-IC/TSV、Cu-Cuハイブリッド接合、各種インターポーザ、FOWLP、マイクロLED、フレキシブルデバイス等に関連したプロセス技術・材料技術の発表を中心にハイライトや最近の動向を紹介いたします。ECTC2021の総発表件数346件のうち1/4以上にあたる88件の発表をピックアップして解説する予定です。

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近年、特に話題を集める半導体後工程ですが、これに関連した数ある国際会議の中でも最も大きく最新の技術が発表されるのがECTC (Electronic Components and Technology Conference) です。今回のセミナーでは、2021年7月に終えたECTC2021の中からチップレット、3D-IC/TSV、Cu-Cuハイブリッド接合、各種インターポーザ、FOWLP、マイクロLED、フレキシブルデバイス等に関連したプロセス技術・材料技術の発表を中心にハイライトや最近の動向を紹介します。ECTC2021の総発表件数346件のうち1/4以上にあたる88件の発表をピックアップして解説する予定です。 　半導体パッケージング技術最大の国際会議ECTC、特に今回はECTC2021で発表された研究内容を多く取り上げ、関連する技術の背景や他の技術との比較も含めて、その特長や技術の進展について初心者でも分かりやすく説明します。

  1. ECTCの紹介と最近の研究動向、および用語の説明
    1. ECTCの発表件数の推移や国別/研究機関別投稿状況
    2. TSV技術 (Via-middle v.s Via-last, Wafer-on-Wafer v.s Chip-on-Wafer他)
    3. InFO (Integrated Fan-Out) とCoWoS (Chip-on-Wafer-on-Substrate)
  2. チップレット 9件
    1. Session 1: 2D and 3D Chiplets Interconnects in FO-WLP/PLP
      1. Paper 1. Die Embedding Challenges for EMIB Advanced Packaging Technology 【Intel】
      2. Paper 2. Advanced HDFO Packaging Solutions for Chiplets Integration in HPC Application 【ASE】
    2. Session 3: Advanced Heterogenous Chiplet and Integration for HPC
      1. Paper 1. A Wafer Level System Integration of the Fifth Generation CoWoS-S with High Performance Si Interposer at 2500 mm2 【TSMC】
      2. Paper 7. Scaling M-Series™ for Chiplets 【Deca Technologies】
    3. Session 4: Heterogeneous Integration Using 2.xD/3D Packaging Technologies
      1. Paper 1. InFO_oS (Integrated Fan-Out on Substrate) Technology for Advanced Chiplet Integration 【TSMC】
      2. Paper 7. Chiplets in Wafers (CiW)-Process Design Kit and Demonstration of High-Frequency Circuits with GaN Chiplets in Silicon Interposers 【HRL Laboratories】
    4. Session 8: Chiplet Integration and Fan-Out Interconnections
      1. Paper 5. Ultra-High Strength Cu-Cu Bonding under Low Thermal Budget for Chiplet Heterogeneous Applications 【National Chiao Tung Univ.】
    5. Session 12: Flexible Interconnects and Low-Temperature Sintering
      1. Paper 4. High-speed, High-density, and Highly manufacturable Cu-filled Through-Glass-Via Channel (Cu bridge) for Multi-chiplet Modules 【DNP】
    6. Session 28: High-speed Signal Integrity and Interconnections
      1. Paper 4. Design and Development of High Density Fan-Out Wafer Level Package (HD-FOWLP) for Deep Neural Network (DNN) Chiplet Accelerators using Advanced Interface Bus (AIB) 【IME】
  3. 3D-IC/TSV 14件
    1. Session 4: Heterogeneous Integration Using 2.xD/3D Packaging Technologies
      1. Paper 6. TSV-Last Integration to Replace ASIC Wire Bonds in the Assembly of X-ray Detector Arrays 【Micross】
    2. Session 7: 3D TSV and Interposer
      1. Paper 1. Heterogenous Integration of Silicon Ion Trap and Glass Interposer for Scalable Quantum Computing Enabled by TSV, Micro-bumps, and RDL 【IME】
      2. Paper 2. Pre-bond Qualification of Through-Silicon Via for the Application of 3-D Chip Stacking 【United Microelectronics Corporation】
      3. Paper 3. 3D Die-Stack on Substrate (3D-DSS) Packaging Technology and FEM Analysis for 55um-75um Mixed Pitch Interconnections on High Density Laminate 【IBM】
      4. Paper 5. Monitoring of the Effect of Thermal Shock on Crack Growth in Copper Through-Glass Via Substrates 【Corning】
      5. Paper 7. A TSV-Last Approach for 3D-IC Integration and Packaging using WNi Platable Barrier Layer 【Tohoku Univ.】
    3. Session 16: Innovation on Bonding and Hybrid Bonding Materials and Processing
      1. Paper 1. One-Step TSV Process Development for 4-Layer Wafer Stacked DRAM 【IME】
      2. Paper 6. Non Conductive Film Analysis Using Cure Kinetics and Rheokinetics for Gang Bonding Process for 3DIC TSV Packaging 【Samsung Electronics】
    4. Session 19: Enhanced Reliability Characterization and Methodologies
      1. Paper 6. Automated Void Detection in TSVs from 2D X-Ray Scans using Supervised Learning with 3D X-Ray Scans 【Institute for Infocomm Research】
    5. Session 25: Advances in Assembly Methods
      1. Paper 3. CoW Package Solution for Improving Thermal Characteristic of 3D TSV-SiP for AI-Inference 【Samsung Electronics】
    6. Session 32: Novel Approaches for Reliability and Process Modeling
      1. Paper 7. A Development of Finite Element Analysis Model of 3DIC TSV Package Warpage Considering Viscoelasticity with Cure-Kinetics 【Samsung Electronics】
    7. Session 33: Flexing and Warpage Characterization and Modeling
      1. Paper 7. Novel Method of Wafer-Level and Package-Level Process Simulation for Warpage Optimization of 2.5D TSV 【Samsung Electronics】
    8. Session 43: Manufacturing Techniques for Emerging Packaging Requirements
      1. Paper 4. Method for Improving Chip Crack and Warpage in Stacked 3D TSV Packaging Structure 【Samsung Electronics】
    9. Session 40: Materials and Techniques in High-Speed Interconnects
      1. Paper 6. Development of Cu Seed Layers in Ultra-High Aspect Ratio Through-Silicon-Vias (TSVs) with Small Diameters 【Beijing Institute of Technology】
  4. Cu-Cuハイブリッド接合 (一部はんだマイクロバンプ接合も含む) 28件
    1. Session 1: 2D and 3D Chiplets Interconnects in FO-WLP/PLP
      1. Paper 7. Enabling D2W / D2D Hybrid Bonding on Manufacturing Equipment Based on Simulated Process Parameters 【Fraunhofer IZM-ASSID】
    2. Session 9: Advances in Cu Bonding
      1. Paper 1. Low Temperature Wafer-to-Wafer Hybrid Bonding by Nanotwinned Copper 【ITRI】
      2. Paper 3. Low Temperature Cu-Cu Bonding with Electroless Deposited Metal Passivation for Fine-Pitch 3D Packaging 【National Chiao Tung Univ.】
      3. Paper 4. Low Temperature Hybrid Bonding for Die to Wafer Stacking Applications 【Xperi】
      4. Paper 5. Low-Temperature All-Cu Interconnections Formed by Pressure-Less Sintering of Cu Pillars with Nanoporous-Cu Caps 【Georgia Tech】
    3. Session 10: Surface Preparation for Cu Bonding
      1. Paper 1. Plasma Activated Low-temperature Die-level Direct Bonding with Advanced Wafer Dicing Technologies for 3D Heterogeneous Integration 【IBM】
      2. Paper 2. Multi-stack Wafer Bonding Demonstration utilizing Cu to Cu Hybrid Bonding and TSV Enabling Diverse 3D Integration 【Samsung Electronics】
      3. Paper 3. In-Depth Parametric Study of Ar or N2 Plasma Activated Cu Surfaces for Cu-Cu Direct Bonding 【Nanyang Technological Univ.】
      4. Paper 4. Dielectric Materials Characterization for Hybrid Bonding 【IME】
      5. Paper 5. Hybrid Bonding of Nanotwinned Copper/Organic Dielectrics with Low Thermal Budget 【National Chiao Tung Univ.】
      6. Paper 6. Comprehensive Study on Chip to Wafer Hybrid Bonding Process for Fine Pitch High Density Heterogeneous Applications 【IME】
      7. Paper 7. Feasibility Study of Nanotwinned Copper and Adhesive Hybrid Bonding for Heterogeneous Integration 【ITRI】
    4. Session 11: Advanced Chip to Chip/Package Interconnections for 3D and Heterogeneous Integration
      1. Paper 1. Scaling Solder Micro-Bump Interconnect Down to 10 μm Pitch for Advanced 3D IC Packages 【Intel】
      2. Paper 2. Fluxless Bonding of Large Area (≥ 900 mm2) Dies-Opportunities and Challenges. 【Kulicke & Soffa】
      3. Paper 4. Towards 5µm Interconnection Pitch with Die-to-Wafer Direct Hybrid Bonding 【CEA-LETI】
      4. Paper 5. Development of Hybrid Bonding Process for Embedded Bump Structure with Cu-Sn/BCB Structure 【Tsinghua Univ.】
      5. Paper 6. Comparison of 3D Packages with 20µm Bump Pitch Using Reflow Soldering and Thermal Compression Bonding 【Siliconware Precision Industries】
      6. Paper 7. Copper to Gold Thermal Compression Bonding in Heterogenous Wafer-Scale Systems 【UCLA】
    5. Session 16: Innovation on Bonding and Hybrid Bonding Materials and Processing
      1. Paper 2. A Novel Photosensitive Polyimide Adhesive Material for Hybrid Bonding Processing 【HD Microsystems】
      2. Paper 4. Development of a Temporary Bonding Tape Having over 300 degC Thermal Resistance for Cu-Cu Direct Bonding 【Sekisui Chemical】
      3. Paper 5. Investigation of Wet Pretreatment to Improve Cu-Cu Bonding for Hybrid Bonding Applications 【National Chiao Tung Univ.】
    6. Session 23: Heterogeneous Integration Processes and Manufacturing
      1. Paper 1. Hybrid Bonding Interconnect for Advanced Heterogeneously Integrated Processors 【Intel】
    7. Session 24: Fan-Out Wafer Level Packaging Developments and Applications
      1. Paper 1. Multi-Tier N=4 Binary Stacking, Combining Face-to-Face and Back-to-Back Hybrid Wafer-to-Wafer Bonding Technology 【IMEC】
    8. Session 38: Reliability Analysis of New Materials in Modern Packaging
      1. Paper 3. Novel Characterization Method of Chip level Hybrid Bonding Strength 【Samsung Electronics】
      2. Paper 6. Mechanical Characterization of Benzene cyclobutene (BCB) Used in Cu/polymer Hybrid Bonding 【Univ. of Maryland】
    9. Session 43: Manufacturing Techniques for Emerging Packaging Requirements
      1. Paper 2. Demonstration of a Collective Hybrid Die-to-Wafer Integration Using Glass Carrier 【IMEC】
      2. Paper 3. Die to Wafer Hybrid Bonding and Fine Pitch Considerations 【Xperi】
      3. Paper 7. Characterization of Bonding Activation Sequences to Enable Ultra-Low Cu/SiCN Wafer Level Hybrid Bonding 【IMEC】
  5. 各種インターポーザ 6件
    1. Session 4: Heterogeneous Integration Using 2.xD/3D Packaging Technologies
      1. Paper 4. 2.2D Die last Integrated Substrate for High Performance Applications 【SiPlus】
    2. Session 5: Technologies for Advanced Substrates and Flip-Chip Bonding
      1. Paper 1. Miniaturized 3D Functional Interposer Using Bumpless Chip-on-Wafer (COW) Integration with Capacitors 【Tokyo Tech】
    3. Session 8: Chiplet Integration and Fan-Out Interconnections
      1. Paper 6. Cost Effective 2.3D Packaging Solution by Using Fanout Panel Level RDL 【Samsung Electronics】
    4. Session 13: Dielectric Materials for High-Speed Wireless Communications
      1. Paper 6. Development of Highly Reliable Crack Resistive Build-up Dielectric Material with Low Df Characteristic for Next-Gen 2.5D Packages 【Sekisui Chemical】
    5. Session 17: Latest Trends in Fan-Out Packaging and Substrate Technology
      1. Paper 2. Reliability Performance of Advanced Organic Interposer (CoWoS®-R) Packages 【TSMC】
    6. Session 23: Heterogeneous Integration Processes and Manufacturing
      1. Paper 3. Improving FC Process for Large 2.5D Molded Interposer 【Samsung Electronics】
  6. FOWLP 20件
    1. Session 1: 2D and 3D Chiplets Interconnects in FO-WLP/PLP
      1. Paper 2. Package Design Optimization of the Fan-out Interposer System 【Samsung Electronics】
      2. Paper 4. SoIS-An Ultra Large Size Integrated Substrate Technology Platform for HPC Applications 【TSMC】
    2. Session 2: Wafer/Panel Level System Integration and Process Advances
      1. Chip-Last HDFO (High Density Fan-Out) Interposer PoP 【Amkor】
    3. Session 3: Advanced Heterogenous Chiplet and Integration for HPC
      1. Paper 1. Analysis on Distortion of Fan-Out Panel Level Packages (FOPLP) 【Samsung Electronics】
      2. Paper 2. S-Connect Technology: Multi-chip, Fan-Out Interposer for Next-Generation, Heterogeneous Integration 【Amkor】
    4. Session 6: Advanced Optoelectronics Packaging
      1. Paper 4. FOWLP and Si Interposer for High Speed Photonic Packaging 【IME】
    5. Session 8: Chiplet Integration and Fan-Out Interconnections
      1. Paper 1. A Novel Wafer-level Packaging Technology: A Key Enabler for New-era High-performance Computing 【Samsung Electronics】
      2. Paper 2. The Dynamic Behavior of Electromigration in a Novel Cu Tall Pillar/Cu Via Interconnect for Fan-Out Packaging 【National Cheng Kung Univ.】
      3. Paper 4. Advances in Photosensitive Polymer Based Damascene RDL Processes: Toward Submicrometer Pitches with More Metal Layers 【IMEC】
      4. Paper 6. Effectiveness of Inorganic Dielectric Layer on Submicron-scale Cu Traces against Thermal Oxidative Stress 【DNP】
      5. Paper 7. Reliability of Chip-Last Fan-Out Panel-Level Packaging for Heterogeneous Integration 【Unimicron】
    6. Session 17: Latest Trends in Fan-Out Packaging and Substrate Technology
      1. Paper 1. Fine RDL Patterning Technology for Heterogeneous Packages in Fan-Out Panel Level Packaging 【Samsung Electronics】
      2. Paper 3. Novel Insulation Materials Suitable for FOWLP and FOPLP 【Ajinomoto】
      3. Paper 4. Versatile Laser Release Material Development for Chip-First and Chip-Last Fan-Out Wafer Level Packaging 【Brewer Science】
      4. Paper 7. Laser Releasable Temporary Bonding Film for Fan-Out Process with Large Panel 【3M】
    7. Session 24: Fan-Out Wafer Level Packaging Developments and Applications
      1. Paper 2. 600mm FOPLP as a Scale Up Alternative to 300mm FOWLP With 6-Sided Die Protection 【NEPES】
      2. Paper 3. Demonstration of Fine Pitch RDL in Fan-Out Panel Level Packaging 【Samsung Electronics】
      3. Paper 4. A Novel Multi-chip Stacking Technology Development Using a Flip-Chip Embedded Interposer Carrier Integrated in Fan-Out Wafer-Level Packaging 【ITRI】
      4. Paper 5. Comprehensive Study of Thermal Impact on Warpage Behaviour of FOWLP with Different Die to Mold Ratio 【IME】
      5. Paper 6. A Novel Chip Placement Technology for Fan-Out WLP using Self-Assembly Technique with Porous Chuck Table 【Lintec】
  7. マイクロLED 4件
    1. Session 5: Technologies for Advanced Substrates and Flip-Chip Bonding
      1. Paper 6. Design, Materials, Process, Fabrication, and Reliability of Mini-LED RGB Display by Fan-Out Panel-Level Packaging 【Unimicron】
    2. Session 16: Innovation on Bonding and Hybrid Bonding Materials and Processing
      1. Paper 3. Development of Simultaneous Transferring and Bonding (SITRAB) Process for μLED Arrays using Anisotropic Solder Paste (ASP) and Laser-Assisted Bonding (LAB) Technology 【ITRI】
    3. Session 35: Emerging Quantum and Advanced Interconnects
      1. Paper 6. Simultaneous Transfer and Bonding (SITRAB) Process for Micro-LEDs Using Laser-Assisted Bonding with Compression (LABC) Process and SITRAB Adhesive 【ITRI】
    4. Session 40: Materials and Techniques in High-Speed Interconnects
      1. Paper 8. Laser Lift Off and Multi Dies Collective Bonding for Inorganic uLED with the Newly Developed Material 【Showa Denko Materials】
  8. フレキシブルデバイス 7件
    1. Session 1: 2D and 3D Chiplets Interconnects in FO-WLP/PLP
      1. Paper 6. FOWLP-Based Flexible Hybrid Electronics with 3D-IC Chiplets for Smart Skin Display 【Tohoku Univ.】
    2. Session 12: Flexible Interconnects and Low-Temperature Sintering
      1. Paper 1. Wafer-Level Flexible 3D Corrugated Interconnect Formation for Scalable In-Mold Electronics with Embedded Chiplets 【Tohoku Univ.】
      2. Paper 2. Printed Stretchable Conductors for Smart Clothing: The Effect of Conductor Geometry and Substrate Properties on Electromechanical Behaviors 【Binghamton Univ.】
    3. Session 17: Latest Trends in Fan-Out Packaging and Substrate Technology
      1. Paper 5. Flexible Two-Layered Photo-Imageable Dielectric and Its Application to Thin Form-Factor and High-Density FPC (Flexible Printed Circuit) Using SAP (Semi-Additive Processes) 【Taiyo Ink】
    4. Session 34: Flexible Hybrid Sensors and Electronics
      1. Paper 1. Nanomanufacturing of Smart and Connected Bioelectronics Through Nanomaterial Printing, Hybrid Material Integration, and Soft Packaging 【Georgia Tech】
      2. Paper 2. Assembly Development of a Highly Flexible and Biocompatible Optoelectronic Neural Stimulator for Implantable Retinal Prosthesis 【Nanovision Biosciences】
      3. Paper 3. Flexible Heterogeneously Integrated Low Form Factor Wireless Multi-channel Surface Electromyography (sEMG) Device 【UCLA】
      4. Paper 4. Wireless Photonic Sensors with Flex Fan-Out Packaged Devices and Enhanced Power Telemetry 【Florida International Univ.】

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